1. Field of the Invention
This invention relates to an apparatus for interrupt detection and arbitration utilized in a system which comprises a plurality of processing circuit modules (including a CPU module) connected to each other by bus lines.
Further, this invention relates especially to an apparatus which detects a plurality of interrupts from a plurality of interrupt source circuit modules, arbitrates a single interrupt destination circuit module, and notifies the interrupt destination circuit module of the plurality of interrupts utilizing two bus cycles.
2. Brief Description of the Related Art
Recently, non-synchronized networks or distributed processing systems have been utilized in the data communication technology field. One of the most advantageous points of those systems is efficient throughput because of the independence of each processing unit.
FIG. 1 illustrates a general block diagram of a typical example of a conventional distributed data base system 2, which mainly comprises a host computer 4, a memory disk system 6 connected thereto, and two terminal controllers 10a and 10b connected to the host computer 4 via communication lines 8a and 8b respectively.
Further, the terminal controllers 10a and 10b are connected to a distributed processing unit 12 having a local disk unit 18 for processing local processing jobs commonly via communication lines 14a and 14b.
Each of the terminal controllers 10a and 10b has a local area network 16a or 16b respectively. In the local area network 16a, assume that there are n (n; integer, n&gt;2) terminal units, 20-1, 20-2, . . . 20-n and in the local area network 16b, assume that there are m (m; integer, m&gt;2) terminal units 22-1, 22-2, . . . 22-m.
As mentioned above, to realize a high total throughput of the system, some circuit modules in the system, such as terminal controllers 10a, 10b, the distributed processing unit 12, and the terminal units 20-n and 22-m, need independence of processing functions. Therefore, generally, the internal operations of such circuit modules are managed by means of a circuit structure (or a software structure) that is called an "interrupt driven structure" or an "event driven structure".
The terminal unit 20-1 will now be discussed as a typical example to explain the details of conventional interrupt detection and arbitration in circuit modules having the "interrupt driven" or "event driven" structure.
FIG. 2 illustrates a general block diagram of the terminal unit 20-1 illustrated in FIG. 1. The terminal unit 20-1 comprises several conventional circuit modules, such as a bus control module 24, a CPU module 28, a communication control module 30 connected to the network 16a via a communication line 31, a memory module 32, an I/O control module 34 connected to a keyboard 39 and a display 37, and a disk control module 36 connected to a local disk unit 38.
Those circuit modules ar connected each other by a bus 26 and are self-controlled by at least one control circuit, such as a microcomputer or a sequencer unit, included in each circuit module. Further, some circuit modules have memory or register circuits accessible by such control circuit for storing control data or programs for self control.
These circuit modules perform, for example, the following functions:
(1) The communication control module 30 watches the status of the communication line 31. If the communication control module 30 detects a communication data (not shown) on the communication line 31, the communication control module 30 receives the communication data and stores it in a communication buffer (not shown) therein. Assume that the communication data carried on the local network 16a is comprised of signaling data which includes a terminal identification or error correction parity data and substantive data which will be utilized in application software executed by the terminal unit 20-1 itself.
(2) The communication control module 30 analyzes the received communication data. The terminal unit 20-1 has a predetermined identification, and if the signaling data in the received communication data has the same destination identification as the predetermined identification of the terminal unit 20-1, the communication control module 30 disassembles the received communication data to the signaling data and the substantive data. Further, the communication control module 30 performs error correction using the signaling data to verify the obtained substantive data.
(3) After verification, the communication control module 30 transfers the substantive data to a predetermined address of the memory module 32 in it predetermined bus transfer cycle. After that, the communication control module 30 notifies the CPU module 28 of the existence of the substantive data in the memory module 32 by means of an interrupt to the CPU module 28.
(4) When the CPU module 28 detects the interrupt, the CPU module 28 recognizes which module interrupted and conducts a predetermined procedure as to the transferred substantive data at the predetermined address in the memory module 32.
(5) The CPU module 28 executes the predetermined procedure as to the substantial data under the control of the application program in the terminal unit 20-1, and generates reply data, if necessary. The CPU module 28 stores the reply data at another predetermined address in the memory module 32 and notifies the communication control module 32 of the existence of the reply data by an interrupt to the communication control module 30.
(6) The communication control module 30 detects the interrupt and analyzes the destination of the interrupt. If it is for the communication control module 30, the communication control module 30 reads the reply data via the bus 26 in another predetermined bus cycle.
(7) Further, the communication control module 30 adds signaling data or error correction parity data to the reply data and generates another communication data for the reply. The communication control module 30 then sends the communication data to the network via the communication line 31.
To accomplish the above mentioned functions (1)-(7), these circuit modules feature the following hardware and operations for interrupt detection and arbitration.
For easy understanding, FIG. 3 will be used to explain the conventional circuit structure for interrupt detection and arbitration. FIG. 3 has been abstracted from FIG. 2. As shown in FIG. 3, each circuit module has a predetermined unique ID (identification) number, for example, #0, #1, #2, . . . #n, and is connected to the other circuit modules by bus 44, which corresponds to the bus 26 in FIG. 2. A circuit module 42, which has the ID number #0, corresponds to the CPU module 28 in FIG. 2 and the other circuit modules 48-1, 48-2, . . . and 48-j correspond to the other circuit modules in FIG. 2.
In this example, suppose that the circuit module 48-1 corresponds to the communication control module 30 and the circuit module 48-2 corresponds to the memory module 32. Each of circuit modules of 48-1 to 48-j has a respective interrupt line 46-1 to 46-j to notify the circuit module 42 (CPU module) of an interrupt request. The circuit modules of 48-1 to 48-j generate interrupt request signals independently, and also the circuit module 42 (#0) performs its own job independently because the circuit module 42 corresponds to CPU module 28.
If one of the circuit modules, for example, circuit module 48-1 (#1), has a job in the circuit module 48-2 (#2) which is to be executed by the circuit module 42 (#0), the circuit module 48-1 generates an interrupt request signal on the interrupt line 46-1 and puts address data of the job in the circuit module 48-2 in a predetermined register (not shown).
Since the circuit module 42 (#0) can accept only one interrupt request at one time, if the interrupt request is the first interrupt request, it will be accepted. If one of the other circuit modules' interrupts has been accepted, the circuit module 42 (#0) masks other interrupts and the interrupt request signal by the circuit module 48-1 won't be accepted until the completion of the job caused by the other interrupts.
When the circuit module 42 detects the interrupt request signal from the circuit module 48-1 via the interrupt line 46-1, the circuit module 42 reads out the contents of the predetermined register (not shown) in the circuit module 48-1 via the bus 44 and analyzes the contents of the register. After the circuit module 42 recognizes the contents as address data of the circuit module 48-2, the circuit module 42 executes the job at the address in the circuit module 48-2 in a predetermined execution cycle. After completion of the job, the circuit module 42 can accept another interrupt request.
However, the above mentioned conventional system has the following disadvantages.
The number of the interrupt lines depends on the number of the circuit modules. Therefore, it is very difficult to add or delete circuit modules from the system (bus). In other words, a user cannot modify or add new functions to the system since the system is not flexible.
Further, since the CPU module always arbitrates all of the interrupts in the conventional system, the detection and arbitration of the interrupts depends only on the processing power of the CPU module. Therefore, a circuit module cannot make an interrupt request directly to a circuit module other than the CPU module. Further, direct notification of an interrupt from one circuit module to the other circuit module is impossible.